Tuesday, 17 February 2015

An Overview of Low Power Techniques Used in VLSI Projects

Recent issues for integrated circuit design emphasized on Low Power IC design. Therefore to understand the complexity and future trends in Integrated Circuit Design Silicon Mentor thrives towards the VLSI based Low Power projects. Silicon Mentor is an R& D unit in VLSI located in India which supervises researchers /students by providing a healthy research platform. Silicon Mentor have worked upon various techniques in Low power VLSI Domain. Some of them are given in following Chart.

VLSI Projects

In Variable Substrate bias technique for power reduction uses the variation in body biasing which controls the number of charge carriers or the accumulation of charge carriers to form the channel b/w source and drain. Therefore the number of charge carriers is directly proportional to the threshold voltage needed for switching of the current in device and not more than sufficient number of charge carriers automatically decreases the power used in circuit.

The MTCMOS technique uses a pair of high threshold transistors. In which upper circuit contains the high threshold PMOS and lower part contains the High threshold NMOS circuit. These high threshold PMOS and NMOS circuit reduces the leakage in standby mode. At Silicon Mentor we have used the different high threshold Predictive Technology Model cards to achieve this goal.

In power gating and Self Controllable Voltage Level we use the basic control circuitry in upper and lower part of the CMOS circuit to gate the power i.e. to provide a virtual ground and VDD to the main circuit in standby mode. These use a stack of NMOS transistor in pull up and stack of PMOS in pull down network which controls the leakage flow in the standby mode because the stack of NMOS and PMOS in standby mode works as resistive path for it.

Dual Threshold CMOS uses the two types of transistors in which one uses for the high threshold and other for low threshold operation. The sleepy keeper and sleep transistor technique additional sleep PMOS is placed between VDD and pull up network, whereas NMOS transistor is used b/w pull down network and GND. The Feedback Circuit technique is used to retain the output state. The leakage feedback based on sleep approach in which two transistor uses to maintain the logic state.

Thus all of these techniques can be used in VLSI projects.

No comments:

Post a Comment